`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:  X-Speed.com.cn
// Engineer: yansf
// 
// Create Date:    01/17/2024
// Design Name: 
// Module Name:    BypassCtrl 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module BypassCtrl(
//-----------input clk
	Clk, 
	Clk_5ms,  
//-----------reset source
	nRst,
//-----------BYPASS CONTROL
	Bypass_Control, 
//-----------BYPASS CONTROL
	BP_BYPASS_PULSE,
	BP_DC_POWER_EN,
	FPGA_BYPASS_EN,
//-----------ERROR reason input
	bp_vol_error,
	com1_mode_error,
	com2_mode_error,
//-----------ERROR OUTPUT CONCTRL BY SOFTWARE
	error_out_ctrl,
//-----------ERROR OUTPUT SIGNAL TO ERROR TERMINAL
	error_terminal_en,
	r_Rst_Botton_Reseted,
	r_wdt_Reseted,
	nRST_REQ_FrCPU,
	w_total_error
);

input 			Clk;
input			Clk_5ms;
input 			nRst;
input 	 	    Bypass_Control;
input			bp_vol_error;
input			com1_mode_error;
input			com2_mode_error;
input			error_out_ctrl;
input			r_Rst_Botton_Reseted;
input			r_wdt_Reseted;
input			nRST_REQ_FrCPU;
	
output 			BP_BYPASS_PULSE;
output			BP_DC_POWER_EN;
output			FPGA_BYPASS_EN;
output			error_terminal_en;
output			w_total_error;

//---------------global error cause----------------
wire			w_total_error;
assign			w_total_error = bp_vol_error || com1_mode_error || com2_mode_error || r_Rst_Botton_Reseted || r_wdt_Reseted ;

//---------------RS232/RS485 CONSOLE BYPASS CONCTRL-------------------
reg   [11:0]	bypass_pulse_low_cnt;
reg	  [5:0]		bypass_pulse_high_cnt;
reg				bp_flyby_clock;
reg				BP_BYPASS_PULSE;
reg				BP_DC_POWER_EN;
reg				FPGA_BYPASS_EN;

parameter		BYPASS_PULSE_LOW_NUM	= 350;
parameter		BYPASS_PULSE_HIGH_NUM	= 35;

always @(posedge Clk or negedge nRst )
begin
	if(!nRst)
		begin
			bypass_pulse_low_cnt <= 12'b0;
			bypass_pulse_high_cnt <= 6'b0;
			bp_flyby_clock <= 1'b0;
		end
	else
		begin
			case( bp_flyby_clock )
			1'b0:
				begin
					if( bypass_pulse_low_cnt == BYPASS_PULSE_LOW_NUM )
						begin
							bypass_pulse_low_cnt <= 12'b0;
							bp_flyby_clock <= 1'b1;
						end
					else
						begin
							bp_flyby_clock <= 1'b0;
							bypass_pulse_low_cnt <= bypass_pulse_low_cnt + 1'b1;
						end		
				end
			1'b1:
				begin
					if( bypass_pulse_high_cnt == BYPASS_PULSE_HIGH_NUM )
						begin
							bypass_pulse_high_cnt <= 6'b0;
							bp_flyby_clock <= 1'b0;
						end
					else
						begin
							bp_flyby_clock <= 1'b1;
							bypass_pulse_high_cnt <= bypass_pulse_high_cnt + 1'b1;
						end		
				end
			default :  ;
			endcase
		end
end


always @(posedge Clk or negedge nRst)
begin
	if(!nRst)
		begin
			BP_BYPASS_PULSE <= 1'b0;
			BP_DC_POWER_EN	<= 1'b0;
			FPGA_BYPASS_EN  <= 1'b0;
		end
	else
		if( w_total_error == 1'b1 )
			begin
				BP_BYPASS_PULSE <= 1'b0;
				BP_DC_POWER_EN	<= 1'b0;
				FPGA_BYPASS_EN  <= 1'b0;
			end
		else
			begin
				if( Bypass_Control == 1'b1 )
					begin
						BP_DC_POWER_EN <= 1'b0;
						BP_BYPASS_PULSE <= 1'b0;
						FPGA_BYPASS_EN  <= 1'b0;
					end
				else
					begin
						BP_DC_POWER_EN <= 1'b1;
						BP_BYPASS_PULSE <= bp_flyby_clock;
						FPGA_BYPASS_EN  <= 1'b1;
					end
			end
end

//---------------ERROR OUTPUT TERMINAL--------------------
reg				error_terminal_en;


always @( posedge Clk )
begin
	if( w_total_error == 1'b1 )
			begin
				error_terminal_en <= 1'b0;
			end
	else
		if( !nRST_REQ_FrCPU )
			begin
				error_terminal_en <= 1'b1;  // 1'b0: ERROR     1'b1:NORMAL
			end
		else
			begin
				if( error_out_ctrl == 1'b1 )
					begin
						error_terminal_en <= 1'b0; 
					end
				else
					begin
						error_terminal_en <= 1'b1;
					end
			end
end

endmodule